Why does the local_cal_success go high but local_init_done stay low during RTL simulation for the hard memory controller? - Why does the local_cal_success go high but local_init_done stay low during RTL simulation for the hard memory controller? Description When running an RTL simulation for the UniPHY-based hard memory controller in Arria® V or Cyclone® V device, you may find local_cal_success go high but local_init_done stay low. The local_init_done signal is driven by the hard memory controller based on the internally synchronized version of the afi_cal_success input. The local_init_done and local_cal_success signals should have the same behavior. However, they may have different behaviors if the the clock input or reset input for the multi port front-end (MPFE) is not correctly connected. Resolution Make sure the MPFE clock and reset ports are properly connected. Related Articles Timing violation when enable 'Extra Timing Report Clock' in DDR3 UniPHY based controller Custom Fields values: ['novalue'] Troubleshooting N/A False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 13.0.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']