When using the UniPHY-based hard memory controller, why do I see timing violations between the ports on the MPFE block? - When using the UniPHY-based hard memory controller, why do I see timing violations between the ports on the MPFE block? Description You may see timing violations between the ports on the MPFE block using different clock frequencies because the Quartus®II software does not automatically cut these timing paths. Resolution There are no paths between the MPFE ports in the UniPHY-based hard memory controller. The failing paths can be safely cut using either the set_clock_groups or set_false_path SDC commands. Refer to the Quartus® II TimeQuest Timing Analyzer (.PDF) document for more information on the SDC commands. Custom Fields values: ['novalue'] Troubleshooting 1506794850 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']