Why does the R-Tile FPGA IP for Compute Express Link* (CXL*) Type2 Design Example report timing violation when selecting PLD clk frequency as 475Mhz? - Why does the R-Tile FPGA IP for Compute Express Link* (CXL*) Type2 Design Example report timing violation when selecting PLD clk frequency as 475Mhz? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.3, the R-Tile FPGA IP for Compute Express Link* (CXL*) Type2 Design Example might report timing violation when selecting PLD clk frequency as 475MHz. Resolution This problem has no plan to be fixed in the future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15014594356 False ['R-Tile for Compute Express Link Solution'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 23.3 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']