When using the E-Tile Hard IP for Ethernet Intel® FPGA IP 10G/25G PTP variants does the Timing Analyzer report o_sclk signal as an unconstrained clock? - When using the E-Tile Hard IP for Ethernet Intel® FPGA IP 10G/25G PTP variants does the Timing Analyzer report o_sclk signal as an unconstrained clock? Description When using the E-Tile Hard IP for Ethernet Intel® FPGA IP 10G/25G PTP variants , the o_sclk signal is an asynchronous pulse routed through clock network. Timing Analyzer incorrectly identifies the o_sclk signal as a clock source and reports it as an unconstrained clock. Resolution No workaround is required, you can safely ignore this Timing Analyzer analysis of o_sclk as an unconstrained clock. Custom Fields values: ['novalue'] Troubleshooting 18012564112 True ['E-tile Hard IP for Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 19.4 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 DX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']