Arria V Hard IP for PCI Express IP Simulation Requirement for Cadence and ALDEC Simulators - Arria V Hard IP for PCI Express IP Simulation Requirement for Cadence and ALDEC Simulators Description Errors in the Cadence NCSim and ALDEC Riviera-PRO simulators may cause simulation of the Cyclone V Hard IP for PCI Express IP Core to fail. Resolution This issue is fixed in version 13.0 of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.0 11.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']