CRA Interrupt Ports Visible in Arria 10 Hard IP for PCI Express IP Core When CRA Parameter is Disabled - CRA Interrupt Ports Visible in Arria 10 Hard IP for PCI Express IP Core When CRA Parameter is Disabled Description If you configure the Arria 10 Hard IP for PCI Express IP core with Avalon-MM interface or Avalon-MM DMA interface and with the Enable control register access (CRA) Avalon-MM slave port parameter turned off, the CraIrq_o interrupt signal, and in Avalon-MM variations, the RxmIrq_< n > interrupt signals, should not be visible at the top level. However, the signals are available. Resolution This issue has no workaround. You can ignore these interrupt signals. This issue is fixed in version 15.0 of the Arria 10 Hard IP for PCI Express IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['Interrupt', 'PCI Express'] ['FPGA Dev Tools Quartus II Software'] 15.0 14.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']