Warning (12030): Port "reconfig_from_xcvr" on the entity instantiation of "alt_pma_0" is connected to a signal of width 368. The formal width of the signal in the module is 230. The extra bits will be left dangling without any fan-out logic. - Warning (12030): Port "reconfig_from_xcvr" on the entity instantiation of "alt_pma_0" is connected to a signal of width 368. The formal width of the signal in the module is 230. The extra bits will be left dangling without any fan-out logic. Description You may encounter the following warnings with the XAUI PHY IP in Arria® V GZ and Stratix® V devices during the Quartus® II software version 13.1 compilation: Warning (12030): Port "reconfig_from_xcvr" on the entity instantiation of "alt_pma_0" is connected to a signal of width 368. The formal width of the signal in the module is 230. The extra bits will be left dangling without any fan-out logic. Warning (12020): Port "reconfig_to_xcvr" on the entity instantiation of "alt_pma_0" is connected to a signal of width 560. The formal width of the signal in the module is 350. The extra bits will be ignored. These warnings are due to the merging of the reconfiguration interfaces during Quartus II compilation. You may ignore the warnings if your reconfig_from_xcvr and reconfig_to_xcvr port widths between the XAUI PHY IP and the transceiver reconfiguration controller match. Resolution The error messages will be improved in a future version of the Quartus II software. Related Articles What is the correct number of reconfiguration interfaces required for a XAUI PHY IP when using Stratix V, Arria V, and Cyclone V transceiver devices? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1 ['Arria® V GZ FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']