Why does my multichannel 10/25G variant with PTP enabled and the “PTP Channel Placement Restriction” of “EHIP1/3” of the E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP fail in the fitter? - Why does my multichannel 10/25G variant with PTP enabled and the “PTP Channel Placement Restriction” of “EHIP1/3” of the E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP fail in the fitter? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.1.1 and earlier, a multichannel 10/25G variant with PTP enabled and the “PTP Channel Placement Restriction” of “EHIP1/3” for multichannel variants of the E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP will fail in the fitter. The fitter error will take the following form: Error(15744): In atom 'av_top|alt_ehipc3_0|alt_ehipc3_hard_inst|EHIP_CORE.c3_ehip_core_inst' The settings must match one or more of these conditions: ( topology != ELANE_1CH_PTP ) OR ( topology != ELANE_1CH_PTP ) But the following assignments violate the above conditions: topology = ELANE_1CH_PTP In atom 'av_top|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|g_xcvr_native_insts[0].ct3_xcvr_native_inst|inst_ct3_xcvr_channel|inst_ct3_hssi_ehip_lane' Error(15744): The settings must match one or more of these conditions: ( topology != ELANE_1CH_PTP ) OR ( topology != ELANE_1CH_PTP ) But the following assignments violate the above conditions: topology = ELANE_1CH_PTP Resolution To work around this problem, choose the “PTP Channel Placement Restriction” of the “EHIP0/2” option in the GUI and alter the device's pinout accordingly. Custom Fields values: ['novalue'] Troubleshooting 2007758041 False ['E-tile Hard IP for Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 18.1.1 ['Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']