When using the Intel® FPGA P-Tile Avalon® memory-mapped IP for PCI* Express, why is the "PCIe0 Link" tab in GUI missing? - When using the Intel® FPGA P-Tile Avalon® memory-mapped IP for PCI* Express, why is the "PCIe0 Link" tab in GUI missing? Description In v20.1 of the Intel® Quartus® Prime Pro Edition software, the Intel® FPGA P-Tile Avalon® memory-mapped IP for PCI* Express " PCIe0 Link " tab is missing from the IP GUI. This problem prevents the user from enabling or disabling the " Slot Clock " reference clock from the connector. Resolution This problem has been fixed starting in v20.2 of the Intel® Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 14011186254 False ['Avalon-MM Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.2 20.1 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 DX FPGA'] ['novalue'] ['novalue'] ['novalue']