Why does the DQS Delay reported in the TimeQuest Timing Analyzer for my altdq_dqs2 based design not match my requested phase shift? - Why does the DQS Delay reported in the TimeQuest Timing Analyzer for my altdq_dqs2 based design not match my requested phase shift? Description Due to a problem in the Quartus® II software versions 13.1 and earlier, you may see an incorrect DQS phase shift reported in the TimeQuest™ Timing Analyzer when the clock used for your DLL is different to the DQS clock rate. The TimeQuest Timing Analyzer incorrectly calculates the phase shift from the DQS clock frequency rather than the DLL clock frequency. Resolution To work around this problem in the Quartus II software version 13.1, apply the following assignment to your quartus settings file ( .qsf ): set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON This workaround ensures that the requested phase shift is correctly calculated from the DLL clock frequency rather than the DQS clock frequency. This assignment is scheduled to be automatically generated in a future relase of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']