25G Ethernet FPGA IP - The 25G Ethernet IP core implements the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium. This IP core optionally includes unidirectional transport and Reed… Altera, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of… Intel® Arria® 10 GT FPGA Intel® Stratix® 10 GX FPGA The 25G Ethernet IP core implements the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium. The IP core includes an option to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard. The media access control (MAC) client side interface for the 25GE IP core is a 64-bit Avalon streaming interface (Avalon-ST). It maps to one 25.78125 Gbps transceiver. The IP core optionally includes Reed-Solomon Forward Error Correction (FEC) for support of direct attach copper (DAC) cable. The 25G Ethernet Intel FPGA IP core with various optional features is also available as hard IP on Intel Stratix 10 devices with E-Tiles. More details can be found on the E-Tile Hard IP for Ethernet page. Ethernet Access Aerospace ASIC Proto Broadcast Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Transportation Wireless 25G Ethernet FPGA IP Key Features Soft PCS logic that interfaces seamlessly to Stratix 10 FPGA 25.78125 gigabits per second (Gbps) or 10.3125 Gbps serial transceivers Offering Brief No No No Yes Encrypted Verilog Intel® Arria® 10 GT FPGA Intel® Stratix® 10 GX FPGA Yes Yes Offering Brief Production a1JUi0000049UUxMAM What's Included Encrypted Verilog source code Ordering Information IP-25GEUMACPHY; IP-25GEUMACPHYF; IP-25GEUMACPHYFC; IP-25GEUMACPHYFFC Digikey Mouser a1JUi0000049UUxMAM Production Intellectual Property (IP) a1MUi00000BO8twMAD a1MUi00000BO8twMAD 2025-08-28T18:42:48.000+0000 The 25G Ethernet IP core implements the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium. This IP core optionally includes unidirectional transport and Reed-Solomon Forward Error Correction (FEC) for support of direct attach copper (DAC) cable. Altera Solutions