Why does simulation fail when using the Interlaken design example? - Why does simulation fail when using the Interlaken design example? Description Due to a problem in the Interlaken IP Core (2nd Generation), the rx_digitalreset and reset_stat keep toggling when using the modelsim or ncsim simulation environment. As a result, the simulating system can't enter lock status or finish successfully. Resolution This problem does not exist when using the VCS simulation environment. This problem has been fixed starting in version v17.1 of the Intel® Quartus® Prime software. Custom Fields values: ['novalue'] Troubleshooting FB: 492659; False ['Interlaken', 'Interlaken (2nd Generation) IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.1 17.0.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']