Cyclone 10 PLLs -> downscale clocks -> how much possible? - Cyclone 10 PLLs -> downscale clocks -> how much possible? Hi All, I'm working with Cyclone 10 GX, which has a reference clock of 100MHz . What lowest frequency could I reach with PLLs using this clock as a reference clock? I've tried to play with Fractional and Integer PLLs and the lowest frequency I succeeded to reach was 3MHz. Is it possible to reach lower frequencies? How can I set cascading of the PLLs? Thank you! Replies: Re: Cyclone 10 PLLs -> downscale clocks -> how much possible? Hello, As per the answer provided by user named 'FvM'. The answer can be accepted. Lower frequencies can be achieved with frequency divider in core logic. Regards, Nazrul Naim Replies: Re: Cyclone 10 PLLs -> downscale clocks -> how much possible? Hi, Thank you for reaching out. Allow me some time to look into your issue. I shall come back to you with findings. Thank you for your patience. Best Regards, Nazrul Naim Replies: Re: Cyclone 10 PLLs -> downscale clocks -> how much possible? Hello, minimal output frequency is definer bei VCO frequency range and output divider factor. It's about 0.6 MHz. Lower frequencies can be achieved with frequency divider in core logic.