Why does the CPRI Intel® FPGA IP Design Example fail to simulate when using the Aldec* Riviera* simulator ? - Why does the CPRI Intel® FPGA IP Design Example fail to simulate when using the Aldec* Riviera* simulator ? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4 and earlier, you might see the CPRI Intel® FPGA IP Design Example fails to simulate when using the Aldec* Riviera* simulator. Resolution There is no workaround for this problem. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Errata 15012619621 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 23.2 22.4 ['Arria® V FPGAs and SoCs', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Agilex™ 7 FPGA F-Series', 'Agilex™ 7 FPGA I-Series', 'Arria® 10 FPGAs and SoCs', 'Stratix® 10 DX FPGA', 'Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 NX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']