Why does the Serial Lite III Streaming FPGA IP design simulation fail using Questa*- FPGA Edition Software version 2023.1? - Why does the Serial Lite III Streaming FPGA IP design simulation fail using Questa*- FPGA Edition Software version 2023.1? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.2, you might observe Verilog and VHDL simulation failures for the Serial Lite III Streaming FPGA IP design with Standard Clocking Mode for the Arria® 10 and Cyclone® 10 devices when using the latest version 2023.1 of Questa*- FPGA Edition Software. Resolution To avoid this simulation failure, you can use the previous Questa*- FPGA Edition Software version 2022.4. Custom Fields values: ['novalue'] Troubleshooting 15013233343 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 23.2 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA'] ['Simulation Dev Tools Questa'] ['novalue'] ['novalue']