DisplayPort Source Designs With Maximum Lane Count 1 Fail Compilation - DisplayPort Source Designs With Maximum Lane Count 1 Fail Compilation Description DisplayPort source designs with maximum lane count set to 1 will fail to compile in the Quartus II software. You will see the following error message: Error (10251): Verilog HDL error at bitec_dp_tx_skew.v(90): index -1 cannot fall outside the declared range [39:0] for dimension 1 of array "data_sr" You will only see this error during the Quartus II software compilation. Your design will pass the ModelSim simulator compilation. Resolution To avoid compilation error, set the maximum lane count to 2 or 4. This issue is fixed in version 16.0 of the DisplayPort IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 16.0 14.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']