Why does the ATX PLL REFCLK switching not work in simulation when using the Stratix V GX Custom or Low Latency PHY in Quartus II Software version 12.0? - Why does the ATX PLL REFCLK switching not work in simulation when using the Stratix V GX Custom or Low Latency PHY in Quartus II Software version 12.0? Description Due to a bug in the simulation model, the ATX PLL REFCLK switching does not work when using the Stratix® V GX Custom or Low Latency PHY in Quartus® II Software version 12.0. Resolution To work around this issue, you can temporarily select the CMU PLL in the PHY MegaWizard™ to simulate REFCLK switching. This issue will be fixed in a future version of Quartus. Custom Fields values: ['novalue'] Troubleshooting novalue False ['PLL'] ['novalue'] novalue novalue ['Stratix® V FPGAs', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue'] - 2021-08-25