How can I dynamically change the Stratix® V Hard IP for PCIe configuration registers' content? - How can I dynamically change the Stratix® V Hard IP for PCIe configuration registers' content? Description The Stratix® V Hard IP for PCI Express® configuration registers' content can be dynamically modified through the Hard IP Avalon® Memory-Mapped (Avalon-MM) reconfiguration interface. Resolution Follow the steps below to use the Avalon-MM reconfiguration interface to access the Hard IP PCIe configuration registers. 1. Instantiate either a lpm_constant or a ROM to source the address to the Hard IP AVMM interface. The attached example design uses a ROM to provide both address and data. 2. Decode the LTSSM state to modify the PCIe configuration register before the link enters L0. 3. Implement a state machine to read/write the desired PCIe configuration register through the Hard IP Avalon-MM interface. Download the StratixVHipReconfig.zip for an example implementation. The state machine that dynamically modifies the PCIe Device ID and Vendor ID is located in the hip_eq_dprio module inside <example_design_path>/pcie_lib/altpcie_hip_256_pipen1b.v. Custom Fields values: ['novalue'] Troubleshooting 85158 False ['Arria® V Hard IP for PCI Express IP'] ['novalue'] novalue novalue ['Arria® V GZ FPGA', 'Stratix® V FPGAs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']