FPGA issue on electronic board - FPGA issue on electronic board
The FPGA is visible via the JTAG probe, and we can program firmware. It seems to run correctly. This is a good point. At this stage, we have tried to implement I2C accesses to configure a clock component on the electronic board and unfortunately, we did not succeed. We observed a strange behaviour on I2C pads. I2C pads are bi-directional pads and implemented in open drain mode : to output a ‘0’ value, pad is configured as output and driven to ‘0’ by internal logic of the FPGA. to output a ‘1’ value, pad is configured as input and signal is driven to ‘1’ by an external pull-up resistor. As the external clock component is not configured (and does not output clocks by default) we use for this firmware As any bi-directional pad, whatever is the pad direction configuration, electrical signal on external IO should always be replicated on <dout>. But it is not the case on one of the banks of our FPGA. To simplify the tests, we have implemented a smaller testcase firmware : 2x bi-directional IOs (SDA and SCL) A weak pull-up (in IO pad) on each of these two IOs (to emulate I2C external pull-up) We have chosen IO which are not routed on the electronic board (NC balls) We performed the test on two different banks (6B and 6D). Both banks are HVIO banks are powered with 1V8. The bi-directional pads behave as expected : io pad signals (driven by <scl_t> and <sda_t>) are replicated on <dout> pins of bidir primitives (<scl_i> and <sda_i>). The bi-directional pads do not work. <dout> pins of bidir primitives (<scl_i> and <sda_i>) are tied to ‘1’. The two designs are 100% identical excepted the pin locations !! We tried to output a clock signal on some IOs pads of the bank 6D configured as output (pins without pull-up neither in pad or on electronic board) and we can observe a clock waveform of 1V8 amplitude on the scope, which means the bank 6D is powered with 1V8. Unfortunately, we currently have only one functional FPGA board. Others should arrive by the end of the week. We are using Quartus Prime Pro 25.3.1 (patch 1.02) What could be the reasons explaining this difference in behaviour between two identical banks ? Could it be : a Quartus tool bug ? a silicium issue ? a bank power supply problem ?
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Re: FPGA issue on electronic board
Background: HVIO stuck at high after configuration Root Cause: RCOMP_GTS pin are left floating Resolution: connect RCOMP_GTS to ground via external resistor (refer KDB) Corrective Action: KDB filed
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Re: FPGA issue on electronic board
Background: HVIO stuck at high after configuration Root Cause: RCOMP_GTS pin are left floating Resolution: connect RCOMP_GTS to ground via external resistor (refer KDB) Corrective Action: KDB filed
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Re: FPGA issue on electronic board
Hi Fabrice, I am closing this case now. regards, Farabi
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Re: FPGA issue on electronic board
Hello Fabrice, thanks for the info. There is latest KDB related to this issue : Why do HVIO pins in an Agilex® 5 or Agilex® 3 FPGA HVIO bank appear to be non-functional after device configuration? | Altera Community - 353565 Hope this helps. regards, Farabi
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Re: FPGA issue on electronic board
Hi Farabi, Thank you for your help. For information the solution has been found for the issue. You can find more detail on the link below Why does the high-voltage I/O (HVIO) input pin stuck at high in Agilex™ 5 FPGA devices? | Altera Community - 338218 Regards, Fabrice
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Re: FPGA issue on electronic board
Hello, Are you able to pullup the I2C signals and see if this can fix the issue? There are internal weak pullup for the IOs but it might be not enough for longer trace I2C signals. regards, Farabi
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Re: FPGA issue on electronic board
Hi Farabi, No there are n pullup for the I2C signal. Do you know if this is a known issue? Thanks Regards, Fabrice
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Re: FPGA issue on electronic board
Hello, In your setup, do you have external pullups for the I2C signals? regards, Farabi
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Re: FPGA issue on electronic board
Hi Farabi, It's OK for sharing you more details No, I am using I2C without HPS Trying to implement I2C accesses to configure a clock component on the electronic board. The test has been performed on two different banks (6B and 6D). Both banks are HVIO banks are powered with 1V8. Find attached the screenshot which highlight the issue SignalTap on bank 6B which works correctly SignalTap on bank 6D which does not work Regards, Fabrice
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Re: FPGA issue on electronic board
Hello, I need more details on your setup in order to help you. 1- Are you using I2C on HPS? 2- What are you trying to achieve? regards, Farabi - 2026-04-17
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