Hold Time Violations for IP Compiler for PCI Express Hard IP Variations on Arria II GZ Devices - Hold Time Violations for IP Compiler for PCI Express Hard IP Variations on Arria II GZ Devices Description IP Compiler for PCI Express hard IP variations that target an Arria II GZ device have hold time violations that affect simulation. The warning is caused by an incorrect timing model setting in the hard IP block for the tl_cfg_sts signals. This issue affects all IP Compiler for PCI Express hard IP variations that target an Arria II GZ device. Resolution This issue has no workaround. This issue is fixed in version 11.0 of the IP Compiler for PCI Express. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 11.0 10.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']