Why does the E-Tile 100G Ethernet Dynamic Reconfiguration Design Example generation fail for both the Intel Agilex® 7 FPGA and the Intel® Stratix®10 FPGA devices? - Why does the E-Tile 100G Ethernet Dynamic Reconfiguration Design Example generation fail for both the Intel Agilex® 7 FPGA and the Intel® Stratix®10 FPGA devices? Description Due to a problem with the Intel® Quartus® Prime Pro Edition Software version 20.1, the E-Tile Hard IP for Ethernet 100G Dynamic Reconfiguration Design Example generation will fail for both the Intel Agilex® 7 FPGA and the Intel® Stratix®10 FPGA devices. Resolution No workaround for this problem exists in version 20.1 of the Intel® Quartus® Prime Pro Edition Software. This problem was fixed in the version 20.2 release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14011304071 True ['Low Latency 100G Ethernet IP for Arria® 10 and Stratix® V'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.2 20.1 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 DX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']