Why does the External Memory Interfaces Intel® Stratix® 10 FPGA IP not calibrate when it is located in the same column as an IOPLL Intel® FPGA IP and the reference clock of the IOPLL Intel® FPGA IP is not ready? - Why does the External Memory Interfaces Intel® Stratix® 10 FPGA IP not calibrate when it is located in the same column as an IOPLL Intel® FPGA IP and the reference clock of the IOPLL Intel® FPGA IP is not ready? Description The IOPLL Intel® FPGA IP will gate the power-up calibration of the External Memory Interfaces Intel® Stratix® 10 FPGA IP if the reference clock of the IOPLL Intel® FPGA IP is not stable. Resolution To work around this problem, follow the steps below: Enable the Connect to an upstream PLL through the Core Clock Network Cascading (create a permit_cal input signal) option in the IOPLL Intel® FPGA IP. Connect the permit_cal input port to 1’b1 in the IOPLL Intel® FPGA IP instance. The power-up calibration of the External Memory Interfaces Intel® Stratix® 10 FPGA IP will be performed regardless of the status of the IOPLL Intel® FPGA IP reference clock. Custom Fields values: ['novalue'] Troubleshooting 15010464582 False ['External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 21.3 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']