Why do I get a fatal error when compiling my Arria V or Cyclone V design? - Why do I get a fatal error when compiling my Arria V or Cyclone V design? Description Due to a problem in the Quartus® II software version 12.1 and later, you may see a fatal error during the Fitter when compiling designs targeting Arria® V or Cyclone® V devices. This problem affects designs with Fast Input Register , Fast Output Register or Fast Output Enable Register assignments if the I/O associated with those assignments are part of a LogicLock™ region. The problem occurs when the LogicLock region extends into the I/O region. For example, this error may occur if your LogicLock region starts at the lower left corner of the device with origin at X0_Y0. Resolution To avoid this problem, adjust your LogicLock region so that it does not extend into the I/O region and only covers core resources. For example, if your LogicLock region starts at the lower left corner of the device, the origin should be at X1_Y1 instead of X0_Y0. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']