Questions about RapidIO II IP core - Questions about RapidIO II IP core Hello! I am trying to use Rapidio II IP core to establish SRIO communication between FPGA and DSP. Here are some questions I have met: Question 1 Are these signals used by users to transmit data packets? Question 2 I notice that these signals belongs to an avalon-st sink. Should I create an avalon-st source by myself to send the data packets to him? If so, must this avalon-st source be created by Qsys or platform designer? Question 3 The signal gen_tx_data is 128bits. Is the maximum bit width of a data packet only 128 bits? Replies: Re: Questions about RapidIO II IP core Hi, I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Replies: Re: Questions about RapidIO II IP core Hi, My questions has already solved because of your answer. I've already accepted your solution. Thank you very much! Regards Replies: Re: Questions about RapidIO II IP core Hi, Just wanted to check with you, is your concern has been addressed? If yes , kindly do let me know. Thank You Regards, Pavee Replies: Re: Questions about RapidIO II IP core Hi, Below is the answers for your questions: Yes, those are the Pass-Through Interface Signals The Avalon-ST pass-through interface is an optional interface that is generated when you select the Avalon-ST pass-through interface in the Transport and Maintenance page of the RapidIO II parameter editor. Yes, only 128 bits. For more details, please refer to Rapid IO II UG. https://www.intel.com/content/www/us/en/docs/programmable/683444/20-3/avalon-st-pass-through-interface-91575.html Regards, Pavee