Is there an known issue with the Early Power Estimator (EPE) tool for Stratix® V, Arria® V, and Cyclone® V devices when estimating off-chip power for Emulated LVDS I/O? - Is there an known issue with the Early Power Estimator (EPE) tool for Stratix® V, Arria® V, and Cyclone® V devices when estimating off-chip power for Emulated LVDS I/O? Description Yes, there is a known issue with the Early Power Estimator (EPE) tool versions 12.1 and earlier for Stratix® V, Arria® V, and Cyclone® V devices, where off-chip power (the power dissipated in the external resistor network) for Emulated LVDS I/O pins is not calculated. Resolution This bug has been fixed in EPE version 13.0 Custom Fields values: ['novalue'] Troubleshooting 2205798098 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.0 12.1 ['Acex® 1K', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']