Why does the Intel® Stratix® 10 MLAB RAM generate unknown output values in gate-level simulation with a VHDL netlist? - Why does the Intel® Stratix® 10 MLAB RAM generate unknown output values in gate-level simulation with a VHDL netlist? Description Due to a problem in the Intel® Stratix® 10 device simulation model in the Intel® Quartus® Prime Pro Edition Software version 19.1 and earlier, you may see unknown (x) MLAB RAM output values in gate-level simulation with the VHDL netlist (*.vho). Resolution To work around this problem, use the Verilog netlist (*.vo) for MLAB RAM in the gate-level simulation. This problem is fixed starting with the Intel® Quartus® Prime Pro/Standard Edition Software version 19.3. Custom Fields values: ['novalue'] Troubleshooting 1408971166 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 18.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']