Why does the 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example simulation run hang? - Why does the 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example simulation run hang? Description Due to a problem in the Intel® Quartus® Prime Pro Edition version 20.1 Software, the design example generated by the 25G Ethernet Intel® Stratix® 10 FPGA IP with dynamic reconfiguration and PTP enabled, will hang when simulated with either Synopsys* VCS* simulator or Cadence* Xcelium*/NCSIM* simulator. Resolution To avoid this problem, user is encounraged to use Mentor* Modelsim* simulator to simulate the design example. This problem is fixed starting from the Intel® Quartus® Prime Pro Edition v20.3 software onwards. Custom Fields values: ['novalue'] Troubleshooting 1507840334 True ['25G Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.3 20.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']