Why is the Low Latency Ethernet 10G MAC FPGA IP TX/RX datapath still enabled when the parameter TX and RX datapath Reset/Default to Enable has been set? - Why is the Low Latency Ethernet 10G MAC FPGA IP TX/RX datapath still enabled when the parameter TX and RX datapath Reset/Default to Enable has been set? Description Due to a mistake in the Low Latency Ethernet 10G MAC FPGA IP User Guide : ID 683426 : Date 8/23/2021: TX and RX datapath Reset/Default to Enable Description is incorrect. It currently reads: Turn on this option to disable TX and RX datapath during startup or CSR reset. It should read: Turn off this option to disable TX and RX datapath during startup or CSR reset. Resolution This problem has been fixed in version 23-3-22-0-3 release of the Low Latency Ethernet 10G MAC FPGA IP User Guide Custom Fields values: ['novalue'] Troubleshooting 18020514747 False ['Low Latency Ethernet 10G MAC IP'] ['FPGA Dev Tools Quartus® Prime Software'] 23.3 21.1 ['Arria® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'Stratix® 10 FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']