Why does the Timing Analyzer display data signals as base clocks in the Clock Network Viewer? - Why does the Timing Analyzer display data signals as base clocks in the Clock Network Viewer? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.2 and earlier, you might see that the Clock Network Viewer in the Timing Analyzer incorrectly displays certain data signals as base clocks. This problem arises when the Timing Analyzer detects an SDC constraint defining a clock that fans out to both data and clock ports. It is important to note that this behavior does not impact the timing analysis of the related paths. This problem only affects Stratix® 10 FPGA devices. Resolution It is safe to ignore clocks originating from data pins, as reported in the Clock Network Viewer. Custom Fields values: ['novalue'] Troubleshooting 14015989290 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 22.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']