What is the fast read timing information for serial configuration devices (EPCS)? - What is the fast read timing information for serial configuration devices (EPCS)? Description The fast read timing information for EPCS16, EPCS64, and EPCS128 configuration devices is shown in the table below. The EPCS1 and EPCS4 do not support the fast read operation. Symbol Parameter Min Max Unit fRCLK Read clock frequency (from FPGA or embedded processor) for read bytes operation — 20 MHz fCLK Fast Read clock frequency — 40 MHz tCH DCLK high time 11 — ns tCL DCLK low time 11 — ns tODIS Output disable time after read — 8 ns tnCLK2D Clock falling edge to data — 8 ns Related Articles Serial Configuration Devices (EPCS) Datasheet: Known Issues Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['Configuration Devices'] ['novalue']