Critical Warning (10169): Verilog HDL warning at alt_mem_ddrx_controller.v(495): the port and data declarations for array port "afi_rrank" & "afi_wrank" do not specify the same range for each dimension - Critical Warning (10169): Verilog HDL warning at alt_mem_ddrx_controller.v(495): the port and data declarations for array port "afi_rrank" & "afi_wrank" do not specify the same range for each dimension Description You may see this critical warning when implementing a DDR2 SDRAM interface using DDR2 SDRAM High Performance Controller II with ALTMEMPHY IP version 12.0. There is a mismatch with the afi_rrank and afi_wrank port size declarations due to parameter not being passed in correctly. However, it will not affect the functionality because afi_rrank and afi_wrank are not used in the DDR2 controller. Resolution This problem was fixed with the Quartus II software version 12.1 and later. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.1 12.0 ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']