Why does the R-tile AXI Streaming IP for PCI Express* Example Design simulation testbench fail to compile in the Quartus® Prime Pro Edition software version 25.1? - Why does the R-tile AXI Streaming IP for PCI Express* Example Design simulation testbench fail to compile in the Quartus® Prime Pro Edition software version 25.1? Description Due to a problem in the 25.1 and earlier versions of the R-Tile AXI Streaming IP for PCI Express*, the example design simulation testbench may fail compilation with the following error: Error-[CFCILFBI] Cannot find cell in liblist ./../..//../../ip/pcie_ss_ed_sim_tb/dut_pcie_tb_ip/intel_rtile_pcie_tbed_100/sim/altpcietb_bfm_rp_gen5_x16_cfbp.sv, 3254 Cell 'pcie_ed_sim_resetIP' cannot be found in liblist for binding instance 'pcie_ss_ed_sim_tb.dut_pcie_tb.dut_pcie_tb.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.u1.rp.inst.resetip'. Resolution To work around this problem, navigate to <generated_ed_path>/pcie_ss_ed_sim_tb/ip/pcie_ss_ed_sim_tb/dut_pcie_tb_ip/intel_rtile_pcie_tbed_100/sim/ and open the file altpcietb_bfm_rp_gen5_x16_cfbp .sv with a text editor. Search for the keyword ' resetIP ' for the line where the resetIP module was instantiated, and change the module name from pcie_ed_sim_resetIP to pcie_ss_ed_sim_resetIP . Before: After: Save the file and re-run the simulation scripts. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 15017583023 False ['R-Tile Avalon-ST for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']