Why is there no output data on o_tx_serial[1:0] pins when only hard reset is applied to F-Tile Ethernet FPGA Hard IP with the '50GE-2' variant? - Why is there no output data on o_tx_serial[1:0] pins when only hard reset is applied to F-Tile Ethernet FPGA Hard IP with the '50GE-2' variant? Description Due to a problem in the Quartus® Prime Pro Edition Software version 22.4 and onward, you may see no output data on o_tx_serial[1:0] pins, and o_tx_ready does not toggle when only hard reset [i_rst_n] is applied to F-Tile Ethernet FPGA Hard IP with '50GE-2' variant. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 22.4 and onward, apply i_tx_rst_n, i_rx_rst_n and csr_rst_n as well as i_rst_n. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16018848969 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.3 22.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']