Warning: Ignored Global Signal option assignment from source signal "PLL output clock name" to destination signal "name"|dll_wys_m -- destination cannot use global signals - Warning: Ignored Global Signal option assignment from source signal "PLL output clock name" to destination signal "name"|dll_wys_m -- destination cannot use global signals Description You may see this warning when you compile a design using DDR3 SDRAM Controller with UniPHY in Quartus ® II software version 11.1SP1 or earlier. This warning can safely be ignored since a global signal assignment is not applied to this dedicated routing from PLL to DLL. The warning is scheduled to be fixed in a future version of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']