Why do the MAC counters of F-Tile Ethernet FPGA Hard IP get stuck at zero when dynamically reconfigured during hardware testing? - Why do the MAC counters of F-Tile Ethernet FPGA Hard IP get stuck at zero when dynamically reconfigured during hardware testing? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.3, the MAC status of F-tile Ethernet FPGA Hard IP is not applicable to the SRC register initial power-on sequence. Hence, the MAC counters get stuck in zero while performing dynamic reconfiguration in the hardware test. Resolution There is no workaround. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Errata 16021975571 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 23.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']