Why does it take several seconds for Active Serial (AS) configuration to complete after power-up of the Cyclone V GT FPGA development kit? - Why does it take several seconds for Active Serial (AS) configuration to complete after power-up of the Cyclone V GT FPGA development kit?
Description Due to the design of the system controller in the MAX® V device, AS configuration is delayed for several seconds after power-up of the Cyclone® V GT FPGA development kit. This delay may cause a problem if your design uses PCI Express (PCIe) and AS configuration mode, as this delay may result in not meeting the PCIe wake-up time requirement. Resolution To reduce the delay of AS configuration in the Cyclone V GT FPGA development kit, program the MAX V device with this Programmer Object File (. pof ) file: max5.pof . You can also use this Quartus® II project : max5_CVGT_devkit_AS.zip for the design in the MAX V device. Related Articles How do I access the EPCQ configuration device on the Cyclone V GT FPGA Development Kit?
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['novalue'] - 2022-01-19
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