Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered - Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered Hello, I would like to confirm the voltages allowed on the Agilex 7 F series Transceiver I/O (the Transceiver Data lanes and the REF_CLK inputs) during power-up or when the Agilex and its transceivers tiles are not powered. For example, I'd like to know if a scenario where Agilex interfaces to an external PCIe host that may drive PCIe clock to the Agilex Transceiver REF_CLK input before it's powered/while it's powering up is acceptable. The requirements for the Agilex GPIO, HPS_IO, and SDM_IO during powerup/when unpowered are clear to me from below documents but not the Transceiver I/O. I don't see any constraints specified for the Transceiver I/O during powerup unless I'm missing it. Can you please confirm this for me, or point me to where this is documented? If it matters, I am interested specifically in F-tile. The A692 Power Sequencing Considerations app note states the below: So it's clear for Cyclone GX, Arria 10, and Stratix 10 L/H tiles that no activity is allowed (with exception of 1.0 Vp-p on Stratix 10) on transceiver I/O during power-up but Agilex is not mentioned in this section. The Agilex 7 General-Purpose I/O User Guide states the following: Table 3: GPIO pin voltage must not exceed VCCIO_PIO or 1.2V, whichever is lower Table 22: HPS I/O pin voltage must not exceed VCCIO_HPS. Table 29: SDM I/O pin voltage must not exceed VCCIO_SDM. I don't see any mention of similar constraint for Transceiver I/O. The Agilex 7 Power Management User Guide states the following: Again, I see all I/O other than Transceiver I/O mentioned. Thanks! Replies: Re: Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered Thanks Ash! Replies: Re: Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered Hi, Yes, there is no footnote about the refclk but they can be driven when unpowered as long as there is proper coupling and the voltages are in the specified limits. Regards Replies: Re: Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered Thank you! I had not noticed the footnotes regarding hot swap on the FGT receivers before. As you comment, I see footnote 97 explicitly calls out the Vin pk-pk for the receviers applies when the part is unpowered. Yes in our application, all lines will be AC coupled. The same footnote about driving lines unpowered does not exist for the FGT REF_CLK inputs (unless I'm missing it), but it seems safe to assume that similar unpowered rating applies to the REF_CLK input as well? Replies: Re: Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered Hi, I got a chance to discuss this topic with my colleagues. The recommendation is to follow the datasheet specifications. Read the footnotes also. https://docs.altera.com/r/docs/683301/current/agilextm-7-fpgas-and-socs-device-data-sheet-f-series-and-i-series/f-tile-transceiver-performance-specifications If you notice, there are recommendations on AC-coupling of the pins. The footnote 97 suggests that the FGT lines can be driven in unpowered state as well, provided the voltage are within the specified limits. Hope this helps. Regards Replies: Re: Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered Thanks Ash. Below image is what I see for Hot Plug capability, indicating that device can be added or removed from system during runtime. It's not clear to me entirely from this that the Transceiver Pins themselves can handle AC voltages (assuming CLK/Data lanes are AC coupled) while the F tile is unpowered/unconfigured or if this assumes the board hardware implements power gating, for example with a buffer on the F tile's PCIe clock input that only propagates the clock to the F tile once the F tile's power rails are present. Replies: Re: Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered Thank you for the link. Below image is what I see regarding hot plug. It states that the device supports addition/removal from system during run-time. I am not sure if this means Hot Plug is supported functionally but assumes the hardware design prevents I/O from being toggled while device is now powered by for example gating the I/O by having an enable for the REF_CLK buffer that is tied to the Agilex power supplies "Power Sequence Done" signal or similar. Can you please confirm Agilex7 F tile transceivers will not be damaged when Agilex 7 F tile hot plugged into system with like PCIe REF_CLK and PCIE data lines such that they are driven before the Agilex7 F tile is powered. Replies: Re: Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered Hi, Specifically for the PCIe application, the F-tile supports the Hot Plug feature. Refer to the following documentation: https://docs.altera.com/r/docs/683140/25.3/f-tile-avalon-streaming-ip-for-pci-express-user-guide/hot-plug I think this is what you were looking for. Regards Replies: Re: Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered It's the F tile. Replies: Re: Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered Hi, May I ask which transceiver tile are you using? Regards