What is the Power supply connection for Pins HPS_Shared_Q2_2 and HPS_Shared_Q4_2 of Arria 10 SoC ? - What is the Power supply connection for Pins HPS_Shared_Q2_2 and HPS_Shared_Q4_2 of Arria 10 SoC ? Description In the Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines document, the connection guideline of Pins HPS_Shared_Q2_2 and HPS_Shared_Q4_2 is as below: "If used as the NAND Ready/Busy input, connect this pin through a 1-10-kΩ pull-up resistor to VCCIO_HPS in the dedicated I/O bank which the NAND_RB pin resides. If unused, program it in the Intel Quartus Prime software as an input with a weak pull-up". This is incorrect, the correct statement should be: "If used as the NAND Ready/Busy input, connect this pin through a 1-10-kΩ pull-up resistor to VCCIO_2L in the dedicated I/O bank which the NAND_RB pin resides. If unused, program it in the Intel Quartus Prime software as an input with a weak pull-up". Resolution This typo is scheduled to be fixed in future Quartus Prime release. Custom Fields values: ['novalue'] Troubleshooting FB: 2007758768; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1.1 16.0 ['Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']