RapidIO IP Core Timing Issues in Stratix IV and Cyclone IV Devices - RapidIO IP Core Timing Issues in Stratix IV and Cyclone IV Devices Description When you compile a RapidIO IP core that targets a Cyclone IV device or a Stratix IV device, you might encounter setup timing violations, especially in the Maintenance module. Resolution To work around this issue, use the standard Quartus II timing strategies of seed sweeping in the Quartus II Design Space Explorer and defining LogicLock regions. This issue will be fixed in a future version of the RapidIO IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']