Incorrect Simulation Models Created for Deinterlacer and Frame Buffer - Incorrect Simulation Models Created for Deinterlacer and Frame Buffer Description The Quartus II software may create incorrect functional simulation models for the Deinterlacer and Frame Buffer MegaCore functions. This issue affects configurations that use a different clock domain for the Avalon Memory-Mapped (Avalon-MM) master interfaces. The IP functional simulation models generated with the MegaWizard Plug-in may reset in an incorrect state. This issue may also affect simulation models generated with SOPC Builder. Resolution If possible, release the reset signals for the Avalon-MM interface ports before the reset signal for the MegaCore function. Alternatively, repeat the generation until the wizard produces a valid . vo or . vho file. This issue will be fixed in a future version of the Video and Image Processing Suite. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']