Is a weak pull-up resistor available on user I/O pins during configuration in Intel® Stratix® 10 devices? - Is a weak pull-up resistor available on user I/O pins during configuration in Intel® Stratix® 10 devices? Description Yes, in Intel® Stratix® 10 devices, user I/O pins are tied to a weak pull-up resistor to the VCCIO of the I/O bank that the pin resides during configuration, after exiting power-on reset until user mode. There is no option to disable the weak pull-up resistor during configuration. Custom Fields values: ['novalue'] Troubleshooting 1507285637 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 17.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']