How do I enable the Loopback Master option of the Intel® Stratix® 10 Hard IP for PCI* Express Root Port? - How do I enable the Loopback Master option of the Intel® Stratix® 10 Hard IP for PCI* Express Root Port? Description Beginning with Intel® Quartus® Prime Pro v18.0 Update 1 software, you can enable Loopback Master option for the Intel® Stratix® 10 Hard IP for PCI* Express Root Port. Resolution To enable the Loopback Master option of the Intel® Stratix® 10 Hard IP for PCI* Express Root Port: Open the IP GUI Right click on the Intel Stratix 10 Hard IP for PCI Express banner and select Show Hidden Parameters Scroll down until you see the Enable Loopback Master option and select it Do not modify any other hidden parameters Right click on the Intel Stratix 10 Hard IP for PCI Express banner and select Hide Hidden Parameters (optional but recommended) Select Generate HDL This Loopback Master function is for link testing only. For normal PCIe* operation, deselect the Loopback Master option, regenerate HDL, and reimplement the design. Custom Fields values: ['novalue'] Troubleshooting FB: 534382; False ['Avalon-MM Stratix® 10 Hard IP for PCI Express', 'Avalon-ST Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.0.1 17.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']