For Fast Passive Parallel (FPP) configuration, if the data is sent in bursts should the clock be paused and the data line be tri-stated during periods without data present? - For Fast Passive Parallel (FPP) configuration, if the data is sent in bursts should the clock be paused and the data line be tri-stated during periods without data present? Description Yes, for FPP configuration it is recommended to pause DCLK and tri-state the data lines for periods of inactivity. If DCLK is still toggling when there is no actual data present, invalid data may be captured. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']