Error (175001): Could not place fractional PLL <PLL name> - Error (175001): Could not place fractional PLL <PLL name> Description When expanding the above error message in the Quartus® II software, you might get the following error message when targeting a Stratix® V, Arria® V, and Cyclone® V device: Error (177020): The PLL reference clock input pin <pin name> was not placed in a dedicated input pin that can reach fractional PLL <PLL name> This error message pair is generated when trying to directly feed a fractional PLL with a CLKn pin. Resolution Place a clock contol block (ALTCLKCTRL megafunction) between the CLKn pin and the input port of the PLL as shown in the example below: Example: Related Articles Error (175020): Illegal constraint of fractional PLL to the region (x-coordinate, y- coordinate) to (x-coordinate, y-coordinate): no valid locations in region Custom Fields values: ['novalue'] Troubleshooting 0000 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] No plan to fix 10.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']