Why do the FEC codeword binning counter registers report inaccurate values for Agilex™ 5 FPGA devices when using the GTS Ethernet Hard IP? - Why do the FEC codeword binning counter registers report inaccurate values for Agilex™ 5 FPGA devices when using the GTS Ethernet Hard IP? Description The FEC codeword binning counter registers ( rsfec_corr_cwbin_cnt_<0 to 11> ) provide inaccurate information for the number of the corrected symbols in a codeword due to a limitation in the Agilex™ 5 FPGA devices. Resolution These registers are no longer supported in the Agilex™ 5 FPGA devices. As an alternative, use the rsfec_lane_rx_hold [31:0] status register to indicate the type of symbols corrected in a codeword. Bit [4]: Set for high symbol error rate. This can be the entire number of codewords in the traffic. Bit [5]: Set for correctable codeword errors. Bit [6]: Set for uncorrected codeword errors. Bit [15:8]: Each bit is set when 15 to 8 symbols are corrected in a codeword (LSB for 8 and MSB for 15 symbols in codeword). Bit [23:16]: Each bit is set when 0 to 7 symbols are corrected in a codeword (LSB for 0 and MSB for 7 symbols in codeword). Example: If rsfec_lane_rx_hold register value is 0x00070030 , represented as 0000 0000 0000 0111 0000 0000 0011 0000 . Additional Information The rsfec_corr_cwbin_cnt_<0 to 11> registers will be removed from a future release of the GTS Ethernet Hard IP Register Map Custom Fields values: ['novalue'] Errata 18039430628 True ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3.1 24.2 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']