PSI5-HOST Peripheral Sensor Interface (PSI5) Host Controller - The PSI5-HOST IP core is a configurable automotive Peripheral Sensor Interface (PSI5) host controller implementing the ECU side of PSI5 communication systems, supporting PSI5 Specification v2.3 with… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA MAX® 10 FPGA Stratix® 10 AX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA The PSI5-HOST IP core is a configurable automotive Peripheral Sensor Interface (PSI5) host controller that implements the ECU side of PSI5 communication systems. The core supports PSI5 Specification v2.3 and is backward compatible with PSI5 v1.3. PSI5-HOST enables robust communication between ECUs and automotive sensors using low-cost two-wire communication over sensor power lines. The core supports both synchronous and asynchronous modes, ECU-to-sensor downstream communication using tooth-gap or pulse-width encoding, and sensor-to-ECU Manchester-coded upstream messaging. The PSI5-HOST architecture incorporates several safety-oriented features, including programmable watchdog timing slots monitoring, receive frame timestamps, and data protection using CRC or parity according to the PSI5 specification. These features allow smooth PSI5-HOST integration into ISO 26262-oriented automotive systems. Access to the PSI5-HOST registers is provided through an AMBA APB register interface. The silicon-proven PSI5-HOST core is designed to industry best practices and has been rigorously verified. Optional functional safety documents and dedicated diagnostic features help developers integrate the core into ISO 26262 safety-related automotive designs. Transportation PSI5-HOST Peripheral Sensor Interface (PSI5) Host Controller Key Features Supported Protocols and Modes: - PSI5 v2.3 and PSI5 v1.3 protocols - 125kbps and 189kbps upstream modes - Synchronous and asynchronous communication Offering Brief No No No Yes Encrypted Verilog Verilog Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA MAX® 10 FPGA Stratix® 10 AX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi000009YfZpMAK What's Included Verilog/System Verilog, Encrypted Verilog/System Verilog or netlist Ordering Information PSI5-HOST a1JUi000009YfZpMAK Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2026-07-16T18:20:04.000+0000 The PSI5-HOST IP core is a configurable automotive Peripheral Sensor Interface (PSI5) host controller implementing the ECU side of PSI5 communication systems, supporting PSI5 Specification v2.3 with backward compatibility to PSI5 v1.3. It enables robust communication between ECUs and automotive sensors using a low-cost two-wire interface over sensor power lines. The core supports synchronous and asynchronous modes, ECU-to-sensor downstream communication via tooth-gap or pulse-width encoding, and sensor-to-ECU Manchester-coded upstream messaging. Safety-oriented features include programmable watchdog timing slot monitoring, receive frame timestamps, and CRC or parity-based data protection per the PSI5 specification, enabling integration into ISO 26262-oriented systems. Register access is performed via an AMBA APB interface. The silicon-proven core is rigorously verified, with optional functional safety documents and diagnostic features aiding ISO 26262 integration. Partner Solutions