HSDLC: HDLC & SDLC Protocol Controller Core - The HSDLC IP core implements HDLC and SDLC protocols, based on the Intel® 8XC152 GSC in SDLC mode with added HDLC and proprietary frame support. It connects as a peripheral to a host processor via… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST SoC FPGA Arria® V SX SoC FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE SoC FPGA Cyclone® V ST SoC FPGA Cyclone® V SX SoC FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA Intel® Cyclone® 10 LP FPGA Intel® MAX® 10 FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® III FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC) protocols. It is based on the Intel® 8XC152 Global Serial Channel (GSC) working in SDLC mode, and adds features to support HDLC or proprietary frame transmission under host processor control. The core operates as a peripheral to a host processor, and is easy to integrate with both modern and legacy processors. Control and status registers are accessible via an APB or a generic 80C51-like bus interface, and a comprehensive set of interrupt signals facilitates interrupt-based operation. The controller’s great flexibility enables a variety of serial link setups. It provides two independent interfaces, one for transmitting and one for receiving data. Both interfaces provide control signals for the link drivers to support both full- and half-duplex operation. The controller can be programmed to use hardware flow control signals (RTS/CTS) and it can also detect collisions. The baud rate is programmable and limited only by the link drivers and the core’s clock frequency. The core derives the receive clock from the received serial data, or uses an externally provided receive clock. The HSDLC is available in two versions: Normal, and Safety-Enhanced. The Safety-Enhanced version implements triple-modular redundancy (TMR) to provide full immunity to single-bit upsets and errors and complies to Design Assurance, Level A (DAL-A) of the DO-254 standard. The HSDLC controller core is designed for reuse and is rigorously verified and scan-ready. Although designed to manage serial links, the core contains no latches or tri-states, and is fully synchronous with a single clock domain. The core is available in Verilog RTL or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation. Communication Aerospace Defense Government Industrial Medical Test Transportation HSDLC: HDLC & SDLC Protocol Controller Core Key Features Controller for SDLC/HDLC (ISO 13239), based on Intel® 8XC152 GSC in SDLC mode, with added support for HDLC & proprietary serial protocols. Offering Brief Yes Yes No Yes Encrypted Verilog Verilog Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST SoC FPGA Arria® V SX SoC FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE SoC FPGA Cyclone® V ST SoC FPGA Cyclone® V SX SoC FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA Intel® Cyclone® 10 LP FPGA Intel® MAX® 10 FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® III FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi0000049U6xMAE What's Included Verilog/System Verilog, Encrypted Verilog/System Verilog, or FPGA netlist Ordering Information HSDLC a1JUi0000049U6xMAE Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2025-09-28T21:20:26.000+0000 The HSDLC IP core implements HDLC and SDLC protocols, based on the Intel® 8XC152 GSC in SDLC mode with added HDLC and proprietary frame support. It connects as a peripheral to a host processor via APB or 80C51-like interfaces, with full interrupt support for efficient operation. Flexible design allows two independent TX/RX interfaces with support for full- or half-duplex, hardware flow control (RTS/CTS), collision detection, and programmable baud rates. Receive clock is derived from incoming data or supplied externally. Available in Normal and Safety-Enhanced (TMR, DO-254 DAL-A) versions, the HSDLC core is fully synchronous, scan-ready, verified, and delivered in Verilog RTL or FPGA netlist. Deliverables include scripts, testbench, and complete documentation. Partner Solutions