Why does my Arria 10 SoC design hang in bootloader or when accessing FPGA-to-SDRAM bridge? - Why does my Arria 10 SoC design hang in bootloader or when accessing FPGA-to-SDRAM bridge? Description Due to a hardware problem, Arria® 10 SoC devices may hang in bootloader, during or after bringing up the SDRAM, or when accessing FPGA-to-SDRAM bridge. The hang can occur: When accessing SDRAM Interconnect When accessing SDRAM memory The issue is very rare, and can occur after power on, cold and warm resets. Resolution The problem is fixed in SoC EDS version 17.0 which is available for download at https://dl.altera.com/soceds/ . A patch for SoC EDS version 16.1 can also be made available upon request. Custom Fields values: ['novalue'] Troubleshooting FB: 391700 420308; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.0 15.0.1 ['Arria® 10 SX FPGA'] ['Embedded Dev Tools SoC Suite'] ['novalue'] ['novalue']