Why does the F-Tile Ethernet Multirate FPGA IP start transmitting invalid packets when the “i_p<n>_tx_rst_n” or “o_p<n>_rst_n” signals are deasserted? - Why does the F-Tile Ethernet Multirate FPGA IP start transmitting invalid packets when the “i_p<n>_tx_rst_n” or “o_p<n>_rst_n” signals are deasserted? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, the F-Tile Ethernet Multirate FPGA IP will transmit invalid packets when the “ i_p<n>_tx_rst_n ” or “ o_p<n>_rst_n ” signals are deasserted If the “ Enable IEEE 1588 PTP ” parameter is set and the “ Link fault generation ” parameter option is set to “ Bidirectional ”. These invalid packets are not driven by the client interface. The packets are typically 64 bytes long and only contain zeroes in all of the fields. Resolution There is no work around to this problem. This problem has been fixed starting in version 24.3 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15016231058 False ['F-Tile Ethernet Multirate IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 23.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']