High Level Synthesis Compiler | Quartus® Prime Design Software - High-Level Synthesis Compiler is an HLS compiler tool that generates production-quality RTL code optimized for Altera® FPGAs. Product Pages Industrial Medical Data Center Cloud Overview The HLS Compiler is a high-level synthesis tool that converts untimed C++ code into optimized, production-quality RTL for Altera® FPGAs. By raising the abstraction level of design input, the HLS Compiler accelerates development and verification cycles compared to traditional RTL design flows. C++ models can typically be verified orders of magnitude faster, enabling more efficient iteration and system-level exploration. The HLS Compiler is included with the Quartus® Prime Pro Edition software installation Overview Features Features Uses untimed ANSI C++ as the golden design source ANSI C++ Design Entry Allows you to quickly explore multiple architectures through high-level directives Architecture Exploration Simplifies tool usage by inferring design intent from high-level constraints Constraint-Driven Design Simplification (1) Simplifies tool usage by inferring design intent from high-level constraints Constraint-Driven Design Simplification (2) Generates reusable intellectual property (IP) for system integration using the Platform Designer IP Generation via Platform Designer Supports inference of streaming, memory mapped, or wire interfaces Interface Type Inference Performs device-specific timing-driven schedule optimization and technology mapping for Altera® FPGAs Timing-Driven Scheduling and Mapping Supports a software compiler use model and industry standards including ac_int data types Compiler Model and Standards Support Detailed reporting feature for a birds-eye view: High-level design HTML reports are automatically generated during the simulation stage Automated HTML Reporting Allows users to view and analyze: Area utilization, loop structure, memory usage, system data flow, clusters, and surrounding logic Design Utilization Insights Supports multiple flows to integrate IP in a system. Integrate HLS code through direct HLD instantiation, through Platform Designer Flexible IP Integration Flows See the Getting Started Guide The HLS Compiler is included in Quartus® Prime Pro Edition. License is required for Quartus® Prime Pro Edition, for licensing information, go to FPGA Licensing Support Center. See more HLS Compiler download and installation information. Getting Started Latest Release Notes Read the release notes Documentation and Support Get Support